The present invention relates to a semiconductor device, and more particularly, to an electrostatic discharge (ESD) protection device for protecting internal circuits from ESD.
ESD is the sudden electric current flowing between two insulating objects when placed under a large electric potentials caused by direct electrical contact.
When a high voltage caused by ESD flows into semiconductor devices, internal circuits may be damaged. Thus, most semiconductor devices include an ESD protection device between a pad and an internal circuit in order for protecting the internal circuit from being damaged.
As semiconductor devices are being operated at higher speeds and highly integrated, a low pin capacitance may be required and a gate dielectric layer is getting thinner.
Junction capacitors of a semiconductor device occupy more than 50% of the pin capacitance. In particular, a parasitic junction capacitance of an ESD protection device located at an input/output pad occupies a significant portion of the pin capacitance. Since the pin capacitance has a negative influence on signal input/output speed and signal retention, a reduction in the pin capacitance is desired in high-speed products. Much effort has been made to reduce a parasitic junction capacitance of an ESD protection device.
One such attempt has been to use a silicon controlled rectifier (SCR) as an ESD protection device that has high ESD efficiency and may reduce parasitic capacitance by a junction region.
Since the junction region of the SCR has an N-well and a P-well, parasitic junction capacitance is small and a large ESD current is discharged even in a small area due to operations of two parasitic bipolar transistors.
However, when an SCR operating at a high voltage is used as an ESD protection device, a gate dielectric layer of an internal circuit may be damaged before operation of the SCR because the gate dielectric layer of the semiconductor device in high-speed, high-integrated products is getting thinner and the breakdown voltage of the gate dielectric layer is also decreasing.
Thus, a low voltage triggered SCR (LVTSCR) operating at a lower voltage than the SCR has been used.
FIG. 1 is a circuit diagram of a typical ESD protection device using an LVTSCR. Referring to FIG. 1, the typical ESD protection device includes an SCR 10 and an NMOS transistor 12. The SCR 10 includes two parasitic bipolar transistors Q1 and Q2 connected between an input/output (I/O) pad and a ground voltage pad VSS in a latch structure. The NMOS transistor 12 is connected between a base of the parasitic bipolar transistor Q2 and the ground voltage pad VSS in order to reduce an operating voltage of the SCR 10.
The typical ESD protection device can reduce the operating voltage down to the breakdown voltage of the NMOS transistor 12, while maintaining a relatively superior ESD effect.
However, when a negative ESD is applied, the typical ESD protection device does not maintain the relatively superior characteristic of SCR.
FIG. 2 is a cross-sectional view of the typical ESD protection device of FIG. 1. Referring to FIG. 2, an N-well 21 is formed in a P-well 20. An NMOS transistor having N-type impurity regions 23 and 25 and a gate 24, and a P-type impurity region 22 for applying a bias voltage to the P-well 20 are formed in the P-well 20. A device isolation layer (STI) is formed between the NMOS transistor and the P-type impurity region 22. N-type impurity regions 25 and 27 and a P-type impurity region 26 are formed in the N-well 21. The N-type impurity region 25 corresponding to a drain of the NMOS transistor is formed over the P-well 20 and the N-well 21.
As illustrated in FIG. 2, a parasitic NPN bipolar transistor Q1 is formed in the P-well 20, and a parasitic PNP bipolar transistor Q2 is formed in the N-well 21. Due to these wells 20 and 21, resistors RP and RN exist.
When excessive ESD is applied to the input/output pad, electron hole pair is generated by junction breakdown in reverse junction of the N-type impurity region 25 and the P-type impurity region 22 having the same potential as the N-well 21. The generated holes move to the P-type impurity region 26, and the generated electrons move to the N-type impurity region 23. Thus, a voltage rise and a voltage drop occur across the resistor RP of the P-well 20 and the resistor RN of the N-well 21, respectively. As a result, the parasitic bipolar transistors Q1 and Q2 are turned on. In this case, even if either of the parasitic bipolar transistors Q1 and Q2 is turned on, the ESD protection device changes to a low impedance state by a positive feedback, and performs an SCR operation to make a large current flow.
However, when negative ESD is applied, parasitic diodes are operated. For example, an excessive ESD voltage may be applied to the ground voltage terminal VSS. In this case, the P-type impurity region 22 functions as an anode, and the N-type impurity region 27 functions as a cathode. Thus, a parasitic diode is formed. Since a current drivability of the diode is inferior to the SCR, the ESD device may not operate normally when a relatively large negative ESD current is applied, resulting in damage of the internal circuit.
That is, although the SCR has a high ESD protection capability, the ESD capability of the SCR may be limited by characteristics of a diode formed when a negative ESD current is applied.